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Hardware Description Languages SIR302-17

ECTS 5 | P 30 | A 0 | L 30 | K 0 | ISVU 175198 205563 | Academic year: 2020./2021.

Course groups

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Course lecturers

MATIĆ TOMISLAV (ml.), Lecturer
ALEKSI IVAN, Lecturer

Overview of course assesment

Learning outcomes
Upon successful completion of the course, students will be able to:

1. define hardware description languages

2. develop and analyse different digital circuits with VHDL and Verilog language

3. distinguish different phases of hardware description processes with VHDL and Verilog languages

4. use Xilinx ISE design suite to simulate and implement described digital circuits

5. design digital circuits with VHDL and Verilog language, demonstrate and test the designed circuit on the available development system



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